Temperature-Aware Floorplanning for Fixed-Outline 3D ICs
نویسندگان
چکیده
منابع مشابه
On Objective Functions for Fixed-Outline Floorplanning
-Fixed-outline floorplanning enables multilevel hierarchical design, where aspect ratios and area of floorplans are usually imposed by higher level floorplanning and must be satisfied. Simulated Annealing is widely used in the floorplanning problem. It is well-known that the solution space, solution perturbation, and objective function are very important for Simulated Annealing. In this paper, ...
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show th...
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show th...
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Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck t...
متن کاملAn iterative merging placement algorithm for the fixed-outline floorplanning
Given a set of rectangular modules with fixed area and variable dimensions, and a fixed rectangular circuit. The placement of Fixed-Outline Floorplanning with Soft Modules (FOFSM) aims to determine the dimensions and position of each module on the circuit. We present a two-stage Iterative Merging Placement (IMP) algorithm for the FOFSM with zero deadspace constraint. The first stage iteratively...
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2019
ISSN: 2169-3536
DOI: 10.1109/access.2019.2942839